From: Paulo Zanoni <paulo.r.zan...@intel.com>
According to the mode set sequence documentation, this is the right
place. According to the FDI_RX_TUSIZE register description, this is
the value we should set.
Signed-off-by: Paulo Zanoni <paulo.r.zan...@intel.com>
---
drivers/gpu/drm/i915/intel_ddi.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 0cb6441..5d33f62 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -196,6 +196,9 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
udelay(600);
+ /* Program PCH FDI Receiver TU */
+ I915_WRITE(_FDI_RXA_TUSIZE1, 0x7E000000);
+
/* Enable PCH FDI Receiver with auto-training */
rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
--
1.7.11.4
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