On Wed, Jan 04, 2012 at 07:40:45PM +0100, Daniel Vetter wrote: > Two things seem to do the trick on my ivb machine here: > - prevent the gt from powering down while waiting for seqno > notification interrupts by grabbing the force_wake in get_irq (and > dropping it in put_irq again). > - ordering writes from the ring's CS by reading a CS register, ACTHD > seems to work. > > Only the blt&bsd ring on ivb seem to be massively affected by this, > but for paranoia do this dance also on the render ring and on snb > (i.e. all gpus with forcewake). > > Tested with Eric's glCopyPixels loop which without this patch scores a > missed irq every few seconds. > > This patch needs my forcewake rework to use a spinlock instead of > dev->struct_mutex. > > v2: Improve the comment per Eugeni Dodonov's suggestion. > > Cc: sta...@kernel.org > Cc: Eric Anholt <e...@anholt.net> > Cc: Kenneth Graunke <kenn...@whitecape.org> > Cc: Eugeni Dodonov <eugeni.dodo...@intel.com> > Tested-by: Eugeni Dodonov <eugeni.dodo...@intel.com> > Reviewed-by: Eugeni Dodonov <eugeni.dodo...@intel.com> > Signed-Off-by: Daniel Vetter <daniel.vet...@ffwll.ch>
>From the internal doc "SNB GT PM Programming Guide", Section 4.3.1: "GT does not generate interrupts while in RC6 (by design)" It talks about the PM interrupt but I think this might also apply to interrupts in general. So I think we should apply the voodoo patch also to snb. My current working theory is hw engineers changed the way hwstam writes are generated wrt to the read/write/irq pipeline on ivb and we've only been lucky that it syncs out everything on snb before the gpu goes into deep sleep states. -Daniel -- Daniel Vetter Mail: dan...@ffwll.ch Mobile: +41 (0)79 365 57 48 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
