On Mon, Oct 03, 2011 at 02:25:39PM -0700, Keith Packard wrote: > On Tue, 20 Sep 2011 15:29:47 -0700, Ben Widawsky <b...@bwidawsk.net> wrote: > > > Add the addresses and definitions I care about for Panel Self Refresh, as > > documented in the eDP spec. > > I generally review the addresses and bit definitions for any new > registers -- getting them wrong makes debugging the code really hard. I > couldn't find these in a brief search through the bspec. Can you point > out where they are? >
This is from the eDP spec, and it turned out there was a bug in this
patch so it's a good thing you check ;). I can resubmit it, but here it
is (copy/paste).
commit 2c15cb896b8b9df3222cde6e011ac113fec84f6f
Author: Ben Widawsky <b...@bwidawsk.net>
Date: Tue Sep 20 12:47:16 2011 -0700
drm: Add Panel Self Refresh DP addresses Add the addresses and
definitions I care about for Panel Self Refresh, as documented in the
eDP spec. I'm sending these out before some other patches because this
should be a fairly simple one to get upstream and not require too much
fuss (where the others may have some fuss). This file is a mess with
white spacing. I tried to stay consistent with the surrounding code.
Cc: linux-ker...@vger.kernel.org
Cc: Dave Airlie <airl...@redhat.com>
Cc: Keith Packard <kei...@keithp.com>
Signed-off-by: Ben Widawsky <b...@bwidawsk.net>
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 91567bb..b49ac6f 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -74,6 +74,18 @@
#define DP_TRAINING_AUX_RD_INTERVAL 0x00e
+#define DP_PSR_SUPPORT 0x070
+# define DP_PSR_SUPPORTED 1
+#define DP_PSR_CAPS 0x071
+# define DP_PSR_TRAIN_ON_EXIT 0
+# define DP_PSR_SETUP_TIME_330 (0 << 1)
+# define DP_PSR_SETUP_TIME_275 (1 << 1)
+# define DP_PSR_SETUP_TIME_220 (2 << 1)
+# define DP_PSR_SETUP_TIME_165 (3 << 1)
+# define DP_PSR_SETUP_TIME_110 (4 << 1)
+# define DP_PSR_SETUP_TIME_55 (5 << 1)
+# define DP_PSR_SETUP_TIME_0 (6 << 1)
+
/* link configuration */
#define DP_LINK_BW_SET 0x100
# define DP_LINK_BW_1_62 0x06
@@ -133,6 +145,12 @@
#define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108
# define DP_SET_ANSI_8B10B (1 << 0)
+#define DP_PSR_EN_CFG 0x170
+# define DP_PSR_ENABLE (1 << 0)
+# define DP_PSR_MAIN_LIKE_ACTIVE (1 << 1)
+# define DP_PSR_CRC_VERIFICATION (1 << 2)
+# define DP_PSR_FRAME_CAPTURE (1 << 3)
+
#define DP_LANE0_1_STATUS 0x202
#define DP_LANE2_3_STATUS 0x203
# define DP_LANE_CR_DONE (1 << 0)
@@ -169,6 +187,21 @@
# define DP_SET_POWER_D0 0x1
# define DP_SET_POWER_D3 0x2
+#define DP_PSR_ERROR_STATUS 0x2006
+# define DP_PSR_LINK_CRC_ERROR (1 << 0)
+# define DP_PSR_RFB_STORAGE_ERROR (1 << 1)
+
+#define DP_PSR_ESI 0x2007
+# define DP_PSR_CAPS_CHANGE (1 << 0)
+
+#define DP_PSR_STATUS 0x2008
+# define DP_PSR_SINK_INACTIVE (1 << 0)
+# define DP_PSR_SINK_ACTIVE_SRC_SYNCED (1 << 1)
+# define DP_PSR_SINK_ACTIVE_RFB (1 << 2)
+# define DP_PSR_SINK_ACTIVE_SINK_SYNCED (1 << 3)
+# define DP_PSR_SINK_ACTIVE_RESYNC (1 << 4)
+# define DP_PSR_SINK_INTERNAL_ERROR (1 << 7)
+
#define MODE_I2C_START 1
#define MODE_I2C_WRITE 2
#define MODE_I2C_READ 4
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