Set both the PM core interrupt regs and the PM specific interrupt maks
to only allow interrupts we handle.  This prevents spurious interrupts
and just makes more sense.

v2: use a mask for the mask reg

Signed-off-by: Jesse Barnes <jbar...@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_reg.h      |    6 ++++++
 drivers/gpu/drm/i915/intel_display.c |   12 ++++--------
 2 files changed, 10 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5baaef4..7033e01 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3442,6 +3442,12 @@
 #define GEN6_RC6p_THRESHOLD                    0xA0BC
 #define GEN6_RC6pp_THRESHOLD                   0xA0C0
 #define GEN6_PMINTRMSK                         0xA168
+#define  GEN6_PMINTR_RP_UP_THRESHOLD           (1<<5)
+#define  GEN6_PMINTR_RP_DOWN_THRESHOLD         (1<<4)
+#define  GEN6_PMINTR_RP_DOWN_EI_EXPIRED                (1<<1)
+#define  GEN6_PMINTR_DEFERRED_EVENTS           (GEN6_PMINTR_RP_UP_THRESHOLD | \
+                                                GEN6_PMINTR_RP_DOWN_THRESHOLD 
| \
+                                                GEN6_PMINTR_RP_DOWN_EI_EXPIRED)
 
 #define GEN6_PMISR                             0x44020
 #define GEN6_PMIMR                             0x44024 /* rps_lock */
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index f6f18c7..00f04b7 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7653,19 +7653,15 @@ void gen6_enable_rps(struct drm_i915_private *dev_priv)
 
        /* requires MSI enabled */
        I915_WRITE(GEN6_PMIER,
-                  GEN6_PM_MBOX_EVENT |
-                  GEN6_PM_THERMAL_EVENT |
                   GEN6_PM_RP_DOWN_TIMEOUT |
                   GEN6_PM_RP_UP_THRESHOLD |
-                  GEN6_PM_RP_DOWN_THRESHOLD |
-                  GEN6_PM_RP_UP_EI_EXPIRED |
-                  GEN6_PM_RP_DOWN_EI_EXPIRED);
+                  GEN6_PM_RP_DOWN_THRESHOLD);
        spin_lock_irq(&dev_priv->rps_lock);
        WARN_ON(dev_priv->pm_iir != 0);
-       I915_WRITE(GEN6_PMIMR, 0);
+       I915_WRITE(GEN6_PMIMR, ~GEN6_PM_DEFERRED_EVENTS);
        spin_unlock_irq(&dev_priv->rps_lock);
-       /* enable all PM interrupts */
-       I915_WRITE(GEN6_PMINTRMSK, 0);
+       /* Enable only those we respond to in the deferred work handler */
+       I915_WRITE(GEN6_PMINTRMSK, ~GEN6_PMINTR_DEFERRED_EVENTS);
 
        gen6_gt_force_wake_put(dev_priv);
        mutex_unlock(&dev_priv->dev->struct_mutex);
-- 
1.7.4.1

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