On Wed, 30 Mar 2011 09:48:25 -0700, Keith Packard <kei...@keithp.com> wrote: > On Wed, 30 Mar 2011 17:07:11 +0100, Chris Wilson <ch...@chris-wilson.co.uk> > wrote: > > > +clear_err: > > + I915_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT); > > + POSTING_READ(GMBUS1 + reg_offset); > > + I915_WRITE(GMBUS1 + reg_offset, 0); > > Any posting read needed here?
I'm not even sure we need the first posting read. Maybe it should be a wait_for(I915_READ(GMBUS1 + reg_offset) & GMBUS_SW_CLR_INT, 100) to be clearer that we are simply giving the hardware the chance to assert the bit and reset before re-enabling. > > + > > +done: > > + I915_WRITE(GMBUS0 + reg_offset, 0); > > What's this new write doing in the non-error path? Do we need a posting > read after it? No, GMBUS0 is not read until the very first phase of the data cycle. And the very first thing we do in the next xfer is a write to GMBUS0 of the port settings. I just thought that explicitly marking the GMBUS controller as disabled when not in use by us would lead to less confusion in future. -Chris -- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
