On Tue, 14 Dec 2010 12:55:59 +0800, Zhenyu Wang <zhen...@linux.intel.com> wrote: > It appears Sandybridge PIPE_CONTROL write out buffer need > to be set as cached, currently LLC cached, in order to read > back correct counter. Otherwise I can always be possible to > get corrupted 64-bit PS_DEPTH_COUNT from PIPE_CONTROL write. > > So below patches try to add new flag during bo create with > cacheable type, to be sure that GTT entry's cache bits would > be setup for that. > > This fixes occlusion query piglit test and mesa demos on my > sandybridge. Note that below patches don't include necessary > component version check changes.
Why don't we just keep all of our BOs LLC cached? This was supposed to be a big win of the new chipset, as it means we don't need to clflush.
pgp8t0k2ZfFV2.pgp
Description: PGP signature
_______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx