We were reading our 64-bit value in I915_READ64 and returning 32 bits
of it. The restoration of fence regs at resume then had a zero end
value, and the fence had no effect.
Signed-off-by: Eric Anholt <e...@anholt.net>
---
drivers/gpu/drm/i915/i915_drv.h | 16 +++++++++++-----
1 files changed, 11 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 73a41f7..f731ecd 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1244,7 +1244,7 @@ extern void intel_overlay_print_error_state(struct
seq_file *m, struct intel_ove
#define I915_READ8(reg) i915_read(dev_priv, (reg), 1)
#define I915_WRITE8(reg, val) i915_write(dev_priv, (reg), (val), 1)
#define I915_WRITE64(reg, val) i915_write(dev_priv, (reg), (val), 8)
-#define I915_READ64(reg) i915_read(dev_priv, (reg), 8)
+#define I915_READ64(reg) i915_read64(dev_priv, (reg))
#define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg))
#define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg))
@@ -1256,12 +1256,9 @@ extern void intel_overlay_print_error_state(struct
seq_file *m, struct intel_ove
static inline u32 i915_read(struct drm_i915_private *dev_priv, u32 reg, int
len)
{
- u64 val = 0;
+ u32 val = 0;
switch (len) {
- case 8:
- val = readq(dev_priv->regs + reg);
- break;
case 4:
val = readl(dev_priv->regs + reg);
break;
@@ -1277,6 +1274,15 @@ static inline u32 i915_read(struct drm_i915_private
*dev_priv, u32 reg, int len)
return val;
}
+static inline u64 i915_read64(struct drm_i915_private *dev_priv, u32 reg)
+{
+ u64 val = readq(dev_priv->regs + reg);
+
+ trace_i915_reg_rw('R', reg, val, 8);
+
+ return val;
+}
+
/* On SNB platform, before reading ring registers forcewake bit
* must be set to prevent GT core from power down and stale values being
* returned.
--
1.7.2.3
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
