On Thu, 28 Oct 2010 16:38:08 +0800, Zhenyu Wang <zhen...@linux.intel.com> wrote: > We should enable FDI normal training on Sandybridge/CPT system > as well. Also restore back some original register posting read > that got removed. LVDS/VGA/HDMI seems back to life but DP still > fails.
The POSTING_READs you added are no-ops since they are all followed by a read. The transconf should have the bpc in the register at this point or else we should have bugged much earlier. The break-exec-wait condition is still documented for gen6, augmented with an additional break-sempahore-wait and obviously per-ring, but this is unrelated to the changelog. I've shrunk the patch to just the FDI portion, pushed to staging for review. Let's try to keep patches as minimal as possible and addressing a single issue. (I'm as guilty of violating that as anyone.) Mostly so that we have a clear history of why/how the code works (and I don't break it later). -Chris -- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
