On Wed, 27 Oct 2010 14:47:32 +0800, Zou Nan hai <nanhai....@intel.com> wrote:
> uxa: enable blt acceleration on gen6 hardware.
That's pretty close to what I had in mind. I thought adding
intel_batch_set_mode(BLT), intel_batch_set_mode(RENDER) etc a bit more
explicit. That gives us a single point at which we can detect a context
switch and perform workarounds, rather than just continuing to add them ad
hoc.
e.g.
static inline void
intel_batch_set_mode(struct intel_screen_private *intel, int mode)
{
if (mode == intel->batch.mode)
return;
intel->batch.context_switch(intel, mode);
intel->batch.mode = mode;
}
static void
gen6_batch_context_switch(struct intel_screen_private *intel,
int mode)
{
intel_batch_flush(intel);
intel->batch.ring = mode;
}
static void
gen5_batch_context_switch(struct intel_screen_private *intel,
int mode)
{
if (intel->batch.mode == BLT) {
OUT_BATCH(3D_NP); /* 2D->3D non-pipeling workaround */
}
intel_batch_flush(intel);
}
void intel_batch_submit(struct intel_screen_private *intel)
{
execbuf.flags |= intel->batch.ring;
...
intel->batch.mode = NONE;
}
etc. [Forgive me the bit of poetic licence in those snippets.] The only
nasty side-effect of that is that you need to perform the
intel_batch_set_mode() in both the prepare and done routines (in case the
batch is emitted before done()).
Btw, why the 32 NOOP workaround? I haven't stumbled across the reason
for that yet.
Your patch works as advertised with just a s/I915_EXEC_BLIT/I915_EXEC_BLT/.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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