On Di 21.Sep'10 at 8:55:44 -0700, Jesse Barnes wrote:
> On Tue, 21 Sep 2010 15:35:27 +0100
> Chris Wilson <ch...@chris-wilson.co.uk> wrote:
>
> > On Tue, 21 Sep 2010 16:22:00 +0200, "Carlos R. Mafra" <crmaf...@gmail.com>
> > wrote:
> > > [ 0.954724] ACPI: Battery Slot [BAT0] (battery present)
> > > [ 2.266008] [drm:intel_lvds_set_power] *ERROR* timed out waiting to
> > > enable LVDS pipeConsole: switching to colour frame buffer device 160x50
> > > [ 2.274860] fb0: inteldrmfb frame buffer device
> > >
> > > But I have this 1+ sec gap in there for as long as I remember.
> > >
> > > Full dmesg is here:
> > > http://www.aei.mpg.de/~crmafra/dmesg-2.6.36-rc5.txt
> > >
> > > Is there anything else I can provide to help this?
> > > I would love to get rid of the 1 sec delay there :-)
> >
> > Sure. Try
> >
> > git://git.kernel.org/pub/scm/linux/kernel/git/ickle/drm-intel.git
> > drm-intel-next
I pulled that branch and tested it. The delay is gone but my external
monitor is not recognized.
[ 0.951319] [drm] Initialized drm 1.1.0 20060810
[ 0.951387] i915 0000:00:02.0: PCI INT A -> GSI 16 (level, low) -> IRQ 16
[ 0.951439] i915 0000:00:02.0: setting latency timer to 64
[ 0.959334] ACPI: Battery Slot [BAT0] (battery present)
[ 1.006415] [drm] initialized overlay support
[ 1.369450] Console: switching to colour frame buffer device 106x30
[ 1.370675] fb0: inteldrmfb frame buffer device
[ 1.370699] drm: registered panic notifier
> Panel power status affects whether other registers (timing, pipe
> control, port) can be written, so not waiting for a power sequence to
> complete can cause problems, so these patches make me a bit nervous.
>
> I wonder why Carlos's power sequence is timing out after a second.
> Maybe we're failing to program a required source bit before starting
> his panel's power on sequence? I ran into this when debugging some eDP
> problems, it turned out we needed some unrelated clocks running just to
> start the panel power sequence. We can either program those clocks
> around the panel power sequence, or possibly write the unlock value
> before trying to turn on the panel.
>
> Carlos, can you try adding
>
> I915_WRITE(ctl_reg, I915_READ(ctl_reg) | PANEL_UNLOCK_REGS);
> POSTING_READ(ctl_reg);
>
> Above the actual write of the POWER_TARGET_ON value? I wonder if it
> will prevent the timeouts you've been seeing.
No, it didn't help. With the diff below on top of 2.6.36-rc5 I get this
[ 0.951730] [drm] Initialized drm 1.1.0 20060810
[ 0.951795] i915 0000:00:02.0: PCI INT A -> GSI 16 (level, low) -> IRQ 16
[ 0.951847] i915 0000:00:02.0: setting latency timer to 64
[ 0.955464] ACPI: Battery Slot [BAT0] (battery present)
[ 1.004349] [drm] set up 7M of stolen space
[ 1.009944] [drm] initialized overlay support
[ 2.765007] [drm:intel_lvds_set_power] *ERROR* timed out waiting to enable
LVDS pipeConsole: switching to colour frame buffer device 160x50
[ 2.773828] fb0: inteldrmfb frame buffer device
[ 2.773830] drm: registered panic notifier
Actual diff below, just to check if I got Jesse's suggestion right.
diff --git a/drivers/gpu/drm/i915/intel_lvds.c
b/drivers/gpu/drm/i915/intel_lvds.c
index 6ec39a8..56b4c0b 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -111,6 +111,8 @@ static void intel_lvds_set_power(struct drm_device *dev,
bool on)
if (on) {
I915_WRITE(lvds_reg, I915_READ(lvds_reg) | LVDS_PORT_EN);
POSTING_READ(lvds_reg);
+ I915_WRITE(ctl_reg, I915_READ(ctl_reg) | PANEL_UNLOCK_REGS);
+ POSTING_READ(ctl_reg);
I915_WRITE(ctl_reg, I915_READ(ctl_reg) |
POWER_TARGET_ON);
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