On Tue, 21 Sep 2010 15:35:27 +0100 Chris Wilson <ch...@chris-wilson.co.uk> wrote:
> On Tue, 21 Sep 2010 16:22:00 +0200, "Carlos R. Mafra" <crmaf...@gmail.com> > wrote: > > [ 0.954724] ACPI: Battery Slot [BAT0] (battery present) > > [ 2.266008] [drm:intel_lvds_set_power] *ERROR* timed out waiting to > > enable LVDS pipeConsole: switching to colour frame buffer device 160x50 > > [ 2.274860] fb0: inteldrmfb frame buffer device > > > > But I have this 1+ sec gap in there for as long as I remember. > > > > Full dmesg is here: > > http://www.aei.mpg.de/~crmafra/dmesg-2.6.36-rc5.txt > > > > Is there anything else I can provide to help this? > > I would love to get rid of the 1 sec delay there :-) > > Sure. Try > > git://git.kernel.org/pub/scm/linux/kernel/git/ickle/drm-intel.git > drm-intel-next Panel power status affects whether other registers (timing, pipe control, port) can be written, so not waiting for a power sequence to complete can cause problems, so these patches make me a bit nervous. I wonder why Carlos's power sequence is timing out after a second. Maybe we're failing to program a required source bit before starting his panel's power on sequence? I ran into this when debugging some eDP problems, it turned out we needed some unrelated clocks running just to start the panel power sequence. We can either program those clocks around the panel power sequence, or possibly write the unlock value before trying to turn on the panel. Carlos, can you try adding I915_WRITE(ctl_reg, I915_READ(ctl_reg) | PANEL_UNLOCK_REGS); POSTING_READ(ctl_reg); Above the actual write of the POWER_TARGET_ON value? I wonder if it will prevent the timeouts you've been seeing. -- Jesse Barnes, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
