charl...@mcn.org (Charles Mills) writes: > It is not possible now. A single instruction may literally add no time at > all to some instruction sequence. > > My imperfect model is that main storage is the new disk. Figure that > instructions take no time at all and memory accesses take forever.
I go even further ... that the current latency to access memory in processor cycles is compareable to 60s letency to access disk in 60s processor cycles (on cache miss). A few decades ago, RISC started doing multi-stage pipeline, concurrent execution (with multiple execution units), out-of-order execution, branch prediction speculative execution, hyperthreading, etc ... in part for offsetting cache misses and inceasing memory access latency (sort of equivalent to 60s software multitasking ... but in the hardware processor). The poster child has been 360/195 & 370/195 that did pipeline with out-of-order execution ... but no branch prediction and speculative execution. I got roped into project to hyperthread 195 (that never shipped). Conditional branches drained the pipeline .... most codes only ran 370/195 at half speed .... because of the stalls associated with conditional branches in most codes, throughput was cut in half. The idea was that simulating two processor (hyperthread) ... each running at half speed, it would achieve full throughput. This is discussion about the end of ACS/360 (executives were afraid that it would advance of the computer state-of-the-art too fast and IBM would loose control of the market) "Sidebar: Multithreading" towards the bottom of the page ... followed by ACS/360 features that show up in ES/9000 some 20-odd years later. Two decades ago, the Intel processors started decomposing Intel instructions into risc micro-ops for actual decoding ... which largely negated the difference between Intel & risc throughput. IBM says that about half the throughput increase from (mainframe) z10 and z196 processors was starting to introduce things like (risc-like) out-of-order execution. -- virtualization experience starting Jan1968, online at home since Mar1970 ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
