[email protected] (Tony Harminc) writes: > It serializes happily against all the CS variations, TS, and the newer > interlocked-update instructions like ASI, LAA, and so on. And there > are cases where a simple ST or the like can interoperate usefully with > CS. For instance, if you update a counter with CS, it is safe to zero > it with ST.
compare-and-swap is atomic instruction ... it does the compare and does the store if the compare matches ... it solves the problem of interrupts and other processes doing something while interrupted. normal process is if the compare doesn't match ... and the store isn't done ... loop back and restart the operation. charlie had invented compare-and-swap while doing fine-grain multiprocessing locking for cp67 at the cambridge science center past posts mentioning science center http://www.garlic.com/~lynn/subtopic.html#545tech ... compare-and-swap was chosen for the name of the instruction because CAS are charlie's initials. past posts mentionin smp and/or compare-and-swap http://www.garlic.com/~lynn/subtopic.html#smp the initial attempt to include compare-and-swap in 370 was rejected because the pok favorite son operating system people said it wasn't needed, that TS was more than sufficient for multiprocessor locking (single kernel spin-lock). the 370 architecture owners said that to get compare-and-swap justified for 370 (over pok objections), had to come up with purposes other than multiprocessor locking. Thus was born the examples (still in principles of operation) for interrupt-enabled, multi-threaded applications (like large dbms) ... whether or not running in multiprocessor configuration or not. -- virtualization experience starting Jan1968, online at home since Mar1970 ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [email protected] with the message: INFO IBM-MAIN
