To locate the failing instruction, look at both IC and ILC. It all works as documented.
IIC? -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר ________________________________________ From: IBM Mainframe Discussion List on behalf of Johnny Luo Sent: Friday, May 2, 2025 11:02 PM To: IBM-MAIN@LISTSERV.UA.EDU Subject: Two different types of 0cx abend External Message: Use Caution Hi, When you execute a "br 14" and r14 contains an invalid address, "br 14" will be successfully executed (and will be recorded in BEAR) and the content of r14 will be loaded into PSW. Then an exception will occur while fetching the next instruction. So in my understanding, an ocx could occur at fetch&decode stage as well as the execution stage. In the former the psw points to the failing instruction. In the latter the psw point to the next instruction, so IlC should be used to get the address of the failing instruction. Is there something wrong with my above thoughts? Thanks. Best Regards, Johnny Luo ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
