Hi, When you execute a "br 14" and r14 contains an invalid address, "br 14" will be successfully executed (and will be recorded in BEAR) and the content of r14 will be loaded into PSW. Then an exception will occur while fetching the next instruction.
So in my understanding, an ocx could occur at fetch&decode stage as well as the execution stage. In the former the psw points to the failing instruction. In the latter the psw point to the next instruction, so IlC should be used to get the address of the failing instruction. Is there something wrong with my above thoughts? Thanks. Best Regards, Johnny Luo ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
