Thanks.
-- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 ________________________________________ From: IBM Mainframe Discussion List [IBM-MAIN@LISTSERV.UA.EDU] on behalf of Joseph Reichman [reichman...@gmail.com] Sent: Sunday, February 19, 2023 9:23 AM To: IBM-MAIN@LISTSERV.UA.EDU Subject: Re: BSAM Read 31 bit mode Shmuel I looked that up or browsed the macro there is no reference rmode/amode 31 in the macro. I did try sysstate amode64 generated the same code. -----Original Message----- From: IBM Mainframe Discussion List <IBM-MAIN@LISTSERV.UA.EDU> On Behalf Of Seymour J Metz Sent: Saturday, February 18, 2023 8:40 PM To: IBM-MAIN@LISTSERV.UA.EDU Subject: Re: BSAM Read 31 bit mode What is on your SYSSTATE? -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 ________________________________________ From: IBM Mainframe Discussion List [IBM-MAIN@LISTSERV.UA.EDU] on behalf of Joseph Reichman [reichman...@gmail.com] Sent: Friday, February 17, 2023 3:35 PM To: IBM-MAIN@LISTSERV.UA.EDU Subject: BSAM Read 31 bit mode Hi I see this documentation from IBM Addressing mode: When you issue the READ macro in 24-bit mode, provide only 24-bit addresses unless you code SF64 or SF64P. When you issue the READ macro in 31-bit addressing mode, provide only 31-bit addresses unless documentation says otherwise or you code SF64 or SF64P. With SF64 or SF64P, the data area can reside above the 2 GB bar but you cannot issue READ in 64-bit mode. And yet my read macro expands to ICM 15,B'0111',49(R6) BALR 14,15 Does the address mode paragraph then mean AMODE 31 RMODE 24 In Addition the synad exit Which has Table 58. Register contents on entry to SYNAD routine-BDAM, BPAM, BSAM, and QSAM Register Bits Meaning 0 0-7 Value to be added to the status indicator's address to provide the address of the first CCW (QSAM only). Value may be zero, meaning unavailable, if LBI is used. Using Non-VSAM User-Written Exit Routines 494 z/OS: z/OS DFSMS Using Data Sets Table 58. Register contents on entry to SYNAD routine-BDAM, BPAM, BSAM, and QSAM (continued) Register Bits Meaning 8-31 Address of the associated data event control block for BDAM, BPAM, and BSAM unless bit 2 of register 1 is on; address of the status indicators shown in Figure 109 on page 491 for QSAM. If bit 2 of register 1 is on, the failure occurred in CNTRL, POINT, or BSP and this field contains the address on an internal BSAM ECB Does this mean The DECB has to be AMODE 24 Thanks ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
