> THe ICM clears bits 0-7 of the (SYNAD?) address. It's the XR that clears bits 0-7, not the ICM.
> It's dismaying that after almost 4 decades programmers must be concerned with > 24-bit limitations. Library macros should be sensitive to some option such as > OPTABLE and generate code accordingly. That's not what OPTABLE is for; many macros test the globals set by SYSSTATE, which is why it's there. > 31-bit is underreaching. Should be 64. Agreed, unless technology advances much more rapidly than I expect. But 24-bit was also underreaching when S/360 came out, given what was already on the market. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 ________________________________________ From: IBM Mainframe Discussion List [IBM-MAIN@LISTSERV.UA.EDU] on behalf of Paul Gilmartin [0000042bfe9c879d-dmarc-requ...@listserv.ua.edu] Sent: Sunday, February 19, 2023 9:37 AM To: IBM-MAIN@LISTSERV.UA.EDU Subject: Re: BSAM Read 31 bit mode On Sun, 19 Feb 2023 12:15:40 +0200, Binyamin Dissen wrote: >The fact that your code is AMODE 31 does not mean that the access method MUST >be above the line. > >The actual expansion had an XR 15,15 before the ICM. > >Why do you think that there is an issue? BALR does not change the AMODE. > With one line more context: >:>ICM 15,B'0111',49(R6) >:> BALR 14,15 THe ICM clears bits 0-7 of the (SYNAD?) address. If the user provides this, it must be below the line; RMODE 24. Will it be called in 24-bit or 31-bit mode? It's dismaying that after almost 4 decades programmers must be concerned with 24-bit limitations. Library macros should be sensitive to some option such as OPTABLE and generate code accordingly. 31-bit is underreaching. Should be 64. >On Fri, 17 Feb 2023 15:35:35 -0500 Joseph Reichman wrote: > >:>I see this documentation from IBM >:> >:>Addressing mode: When you issue the READ macro in 24-bit mode, provide only >:>24-bit addresses unless you code SF64 or SF64P. When you issue the READ >:>macro in 31-bit addressing mode, provide only 31-bit addresses unless >:>documentation says otherwise or you code SF64 or SF64P. With SF64 or SF64P, >:>the data area can reside above the 2 GB bar but you cannot issue READ in >:>64-bit mode. >:> >:>And yet my read macro expands to >:>ICM 15,B'0111',49(R6) >:> BALR 14,15 >:> >:>Does the address mode paragraph then mean AMODE 31 RMODE 24 >:> >:>In Addition the synad exit Which has >:> >:>Table 58. Register contents on entry to SYNAD routine-BDAM, BPAM, BSAM, and >:>QSAM Register Bits Meaning 0 0-7 Value to be added to the status indicator's >:>address to provide the address of the first CCW (QSAM only). Value may be >:>zero, meaning unavailable, if LBI is used. Using Non-VSAM User-Written Exit >:>Routines 494 z/OS: z/OS DFSMS Using Data Sets Table 58. Register contents >:>on entry to SYNAD routine-BDAM, BPAM, BSAM, and QSAM (continued) Register >:>Bits Meaning >:> >:>8-31 Address of the associated data event control block for BDAM, BPAM, and >:>BSAM unless bit 2 of register 1 is on; address of the status indicators >:>shown in Figure 109 on page 491 for QSAM. If bit 2 of register 1 is on, the >:>failure occurred in CNTRL, POINT, or BSP and this field contains the address >:>on an internal BSAM ECB >:> >:>Does this mean The DECB has to be AMODE 24 -- gil ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
