The odds are as close to 100% as anything could get that BALR 14,15 on a
machine *does* behave according to the architecture with respect to
setting register 14.
The system would not stay up for long if the AMODE bit were not properly
represented in the return register. Both BALR 14,15 and BASR 14,15 result
in BSM 0,14 returning to the caller in the correct AMODE.
If what you wrote did happen, your 'real machine" is clearly broken, and
needs to be fixed, so you had better contact hardware support.
So now to a question: you wrote "high order bit". Did you mean bit 32 of
the 64-bit register or bit 0 (i.e., high order bit of 64-bit reg 14 or
high-order bit of 32-bit reg 14)?
Not that betting is appropriate in this regard, but if I were able to do
so, I'd give pretty good odds that the machine is right and that it's your
view that isn't. There was no description of how you saw the incorrect
register 14 or demonstrated that it was incorrect because of the behavior
of BALR..
Regarding reading the table
| | In |Bits | Bit
|Instruction| Format |Mode |0-31 | 32
BALR*/BAL | RR/RX | 24 | U | *** | ***
| | 31 | U | BAM
In Mode: the AMODE in which the instruction is issued.
Bit 32, for "In Mode" (AMODE) 31 is "BAM".
BAM is PSW bit 32, which is on in AMODE 31.
Thus BALR in AMODE 31 results in PSW.32 being on
(Conventional notation "xxx.#" is shorthand for 0-origin xxx bit #)
Peter Relson
z/OS Core Technology Design
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