> -----Original Message-----
> From: IBM Mainframe Discussion List
> [mailto:[email protected]] On Behalf Of Tom Marchant
> Sent: Monday, November 29, 2010 11:11 AM
> To: [email protected]
> Subject: Re: IEFBR14
>
> On Mon, 29 Nov 2010 10:51:19 -0600, Chase, John wrote:
>
> >Wasn't there also a requirement that whatever means was
> chosen to zero
> >Reg15 also set the condition code to zero?
>
> The condition code for the step is set from the value in register 15.
> There is no connection between that and the condition code bits in
> the PSW. No, there was no requirement to set the CC bits in the PSW.
>
> --
> Tom Marchant
Now that would be interesting, tho. Most code does something like:
CALL SOMEPGM,...
LTR 15,15
BNZ ERROR
Imagine if IBM had stated that that subroutine linkage should set the CC as
well as the RC in 15 so that the code could have been shorted to:
CALL SOMEPGM,...
BNZ ERROR
I saved 2 bytes and one instruction. Today, who cares? On an old S/360???
--
John McKown
Systems Engineer IV
IT
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