You might want to use makes -p option (--print-data-base) to print out the targets and prereqs that it has read. The format of this output is simplified - all variables etc are expanded - so in python it's very easy to parse.
Regards, Tim On 5 July 2016 at 23:42, Adrian Muresan <adrianmure...@outlook.com> wrote: > I hoped to spare you details but here goes: > > > I have another `make`-like tool that produces an XML as an artifact after > parsing my makefile which I'll then further process with Python. > > > It'd simplify things for me - a lot - if I could have `make` consider > every single prerequisite to be an actual target because then this other > tool > > will classify each and every file as a <job>. > > > This is a fragment of my makefile: > > > .obj/eventlookupmodel.o: > C:/Users/User1/Desktop/A/PROJ/src/AL2HMIBridge/LookupModels/eventlookupmodel.cpp > C:\Users\User1\Desktop\A\PROJ\src\AL2HMIBridge\LookupModels\eventlookupmodel.h > \ > > C:/Users/User1/Desktop/A/PROJ/qt5binaries/include/QtCore/qabstractitemmodel.h > \ > > C:/Users/User1/Desktop/A/PROJ/qt5binaries/include/QtCore/qvariant.h \ > ... > > > I'd want, implicitly, for `make` to think I have a dummy rule for each > file such as below: > > > C:/Users/User1/Desktop/A/PROJ/qt5binaries/include/QtCore/qvariant.h: > > @echo target pre= $@ > > > > > C:/Users/User1/Desktop/A/PROJ/qt5binaries/include/QtCore/qabstractitemmodel.h: > > @echo target pre=$@ > > > C:/Users/User1/Desktop/A/PROJ/src/AL2HMIBridge/LookupModels/eventlookupmodel.cpp > : > > @echo target pre=$@ > > > > C:\Users\User1\Desktop\A\PROJ\src\AL2HMIBridge\LookupModels\eventlookupmodel.h: > > @echo target pre=$@ > > > Yes, I know that the gcc `-M` options do exactly that but I need to keep > my makefile modifications to a minimum. > > > I don't care about the exact form of the rule just that each file is > considered an actual target. > > > My method of passing in this rule would be by setting the MAKEFILES var > like so > > > make all MAKEFILES=Dummy.mk > > > with Dummy.mk containing this rule so that I do not modify the makefiles. > > > I've tried the following so far. > > Dummy.mk: > > %.h: > @echo header xyz = $@ > > %: > @echo other xyz= $@ > > This partially works. > > I run `make all --trace --print-data-base MAKEFILES=Dummy.mk` and I can > see that > `make` does "bind" the "%.h" rule to the header files. In the > --print-data-base section, > I see that rule being assigned to the header files. However, I do NOT see > "echo header xyz" being executed. > > Example: > > C:/Users/User1/Desktop/A/QNX_SDK/target/qnx6/usr/include/stddef.h: > # Implicit rule search has been done. > # Implicit/static pattern stem: > 'C:/Users/User1/Desktop/A/QNX_SDK/target/qnx6/usr/include/stddef' > # Last modified 2016-05-27 12:39:16 > # File has been updated. > # Successfully updated. > # recipe to execute (from '@$(QMAKE) > top_builddir=C:/Users/User1/Desktop/A/HMI_FORGF/src/../lib/armle-v7/release/ > top_srcdir=C:/Users/User1/Desktop/A/HMI_FORGF/ -Wall CONFIG+=release > CONFIG+=qnx_build_release_with_symbols CONFIG+=rtc_build -o Makefile > C:/Users/User1/Desktop/A/HMI_FORGF/src/HmiLogging/HmiLogging.pro > ', line 2): > @echo header xyz = $@ > > > Regarding the "%" rule, it is neither executed for the .cpp files nor > "bound" to them in the --print-data-base section. > However, it is bound and executed for existing targets which have no > suffix i.e. > > all: library binary > > binary: | library > ifs: | library > > For the `%:` rule, the reason for this behavior is because of "10.5.5 > Match-Anything Pattern Rules" > If I make it non-terminal - no double colon - then the rule doesn't apply > to built-in types like `.cpp` . . . unless I undefine the built-in types > that are caught by this rule. > > If I make it terminal, "it does not apply unless its prerequisites > actually exist". But a `.h` or `.cpp` doesn't technically have > prerequisites; can I just create a dummy file and have that as its > prerequisite? > > > > > > ====================================================================== > It's not clear exactly what you want to do, but no, there is no built- > in function that provides this information. > > Of course, from within a recipe you can use the $^ automatic variable, > which contains all the prerequisites of the current target. > > > I could probably make a rule that will parse the makefile as a > > textfile from the shell but since `make` already parses the targets > > and prereqs I'm hoping there's a built-in way. > > It's not that simple in all cases: for example, make won't attempt to > resolve suffix and pattern rules until it finds a target that needs to > use that rule to build, and so the complete set of prerequisites can't > be known until that time. > > Similarly, new prerequisites could be added to an existing target at > any time, so any list of prerequisites obtained before all makefiles > are parsed will always be suspect. > _______________________________________________ > Help-make mailing list > Help-make@gnu.org > https://lists.gnu.org/mailman/listinfo/help-make > _______________________________________________ Help-make mailing list Help-make@gnu.org https://lists.gnu.org/mailman/listinfo/help-make
