On Tue, 2016-07-05 at 16:50 +0000, Adrian Muresan wrote: > Is there a built-in function to extract all the prerequisites for > target in a makefile?
It's not clear exactly what you want to do, but no, there is no built- in function that provides this information. Of course, from within a recipe you can use the $^ automatic variable, which contains all the prerequisites of the current target. > I could probably make a rule that will parse the makefile as a > textfile from the shell but since `make` already parses the targets > and prereqs I'm hoping there's a built-in way. It's not that simple in all cases: for example, make won't attempt to resolve suffix and pattern rules until it finds a target that needs to use that rule to build, and so the complete set of prerequisites can't be known until that time. Similarly, new prerequisites could be added to an existing target at any time, so any list of prerequisites obtained before all makefiles are parsed will always be suspect. _______________________________________________ Help-make mailing list Help-make@gnu.org https://lists.gnu.org/mailman/listinfo/help-make
