Thanks everyone! I went with the test on MAKECMDGOALS. I had done something like this years ago but my make muscles got rusty.
To digress slightly, I also had a situation where I needed an include file that was generated from a subdirectory that needed to be built by the makefile. I solved it by forcing a re-read of prerequisites using a generated touchfile that was included at the bottom of the Makefile with no text in it: For example: all: foo/.touch $(OTHEREXES) test: all foo/.touch: foo/. <tab> git submodule update --init --recursive $(@D) <tab> cd $(@D); git checkout master; git pull; touch $(@F) special.o: generated.h generated.h: foo/path/to/generator.source # ... other prereqs ... -include foo/.touch Ted On Wed, Nov 18, 2015 at 12:00 AM, Rakesh Sharma <sharma...@hotmail.com> wrote: > What you are asking for can be accomplished using ifeq conditionals, like > as shown below: > > > SHELL := /bin/sh > > WHO_AM_I = $(CURDIR)/$(word 1,$(MAKEFILE_LIST)) > > CC = g++ > CFLAGS = -Wall > LDFLAGS = > > EXESUFF = > SRC = a.cpp > OBJS = a$(EXESUFF).o > RUNFILE = b$(EXESUFF).out > > all : $(RUNFILE) > > $(RUNFILE) : $(OBJS) > $(CC) $(CFLAGS) $(LDFLAGS) $(OBJS) $(LIBS) -o $@ > > $(OBJS) : $(SRC) > $(CC) -c $(CFLAGS) $< -o $@ > > clean : > /bin/rm -f ./*.o ./*.out > > TESTFLAG := _test > test: CFLAGS += -D__TEST__ > ifeq ($(EXESUFF),$(TESTFLAG)) > test: $(RUNFILE) > else > test: > @$(MAKE) --no-print-directory -f $(WHO_AM_I) $@ EXESUFF=$(TESTFLAG) > endif > > > Alternatively, you can use the second expansion facility provided by GNU > make to achieve the same results: > > > .SECONDEXPANSION: > TESTFLAG := _test > test: CFLAGS += -D__TEST__ > test: $$(if $$(EXESUFF),$$(RUNFILE),) > $(if $(EXESUFF),,@$(MAKE) --no-print-directory -f $(WHO_AM_I) $@ > EXESUFF=$(TESTFLAG)) > > -Rakesh > > > > > Hello Paul et al., > > > I'm familiar with target-specific variables and have been using them for > > many years. > > > But they don't seem to be doing what I want in one circumstance -- I want > > to build different target names depending on an inherited target-specific > > variable. > > > For example > > > EXESUFF =# blank to start > > > a$(EXESUFF).o : a.cpp > > <tab> $(CXX) $(CXXFLAGS) -c $< -o $@ > > > OBJS = a$(EXESUFF).o > > > b$(EXESUFF).out : $(OBJS) > > <tab> $(CXX) $(CXXFLAGS) $(LDFLAGS) $(OBJS) $(LIBS) -o $@ > > > all: b.out > > > clean: > > <tab> /bin/rm *.o *.out > > > test: EXESUFF = _test > > test: CXXFLAGS += -D__TEST__ > > > % make all > > > (builds a.o and b.out) > > > % make clean; make test > > > (builds a.o and b.out -- but I want it to build a_test.o and b_test.out) > > > Is there a way to do what I want? > > > Thanks, > > > Ted > > _______________________________________________ Help-make mailing list Help-make@gnu.org https://lists.gnu.org/mailman/listinfo/help-make
