Hello!
I am currently setting up a make file (at least I try) for building a firmware
image for a cortex M4 MCU.
However I am struggeling at this point:
DIR := \
D:/test/
SUBDIRS := \
src/test/usb_cdc_lolevel
C_SRCS := \
$(wildcard $(DIR)src/test/usb_cdc_lolevel/*.c)
OBJS := \
$(patsubst $(DIR)src/test/usb_cdc_lolevel/%.c, ./src/test/usb_cdc_lolevel/%.o,
$(C_SRCS))
C_DEPS := \
$(wildcard ./src/test/usb_cdc_lolevel/*.d)
./src/test/usb_cdc_lolevel/%.o: $(DIR)src/test/usb_cdc_lolevel/%.c
@echo 'Building file: $<'
@echo 'Invoking: Cross ARM C Compiler'
arm-none-eabi-gcc $(CFLAGS) $(INCDIRS) -MMD -MP
-MF"$(@:%.o=%.d)" -MT"$@" -c -o "$@" "$<"
@echo 'Finished building: $<'
@echo ' '
All I want to do is replacing the hardcoded string using a variable I have
defined before, so it looks like:
C_SRCS := \
$(wildcard $(DIR)$(SUBDIRS)/*.c)
OBJS := \
$(patsubst $(DIR)$(SUBDIRS)/%.c, ./$(SUBDIRS)/%.o, $(C_SRCS))
C_DEPS := \
$(wildcard ./$(SUBDIRS)/*.d)
# Each subdirectory must supply rules for building sources it contributes
./$(SUBDIRS)/%.o: $(DIR)$(SUBDIRS)/%.c
@echo 'Building file: $<'
@echo 'Invoking: Cross ARM C Compiler'
arm-none-eabi-gcc $(CFLAGS) $(INCDIRS) -MMD -MP
-MF"$(@:%.o=%.d)" -MT"$@" -c -o "$@" "$<"
@echo 'Finished building: $<'
@echo ' '
These changes throw me an error "*** mixed implicit and normal rules:
deprecated syntax" on line "./$(SUBDIRS)/%.o: $(DIR)$(SUBDIRS)/%.c", already
googled this issue and it seems to happen to quiet some people. As far as I
understand the issue is the "/%" occurance. It's driving me nuts because it
seems I am not able to fix it on my own (I have little to no experience in
writing make files so far)
Any help or hint would be appreciated!
Thank you!
Regards
Christian
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