Hi Pedro, On quick suggestion: It may make sense to put the prefetcher in the CPU model code (e.g., during the decode stage in the O3CPU) instead of in the decode logic of the ISA. After you get the `StaticInst` from the decoder, you should be able to push prefetch requests into the instruction cache from there. Hopefully this helps some.
Cheers, Jason On Wed, Aug 16, 2023 at 11:21 AM Pedro Corrêa Rigotto via gem5-users < gem5-users@gem5.org> wrote: > For my research, I need to do some instruction prefetching during the > decoding step of specific instructions, which are not memory access > instructions. I am using Syscall Emulation mode, and I'm studying the x86, > ARM and RISC-V ISAs, however I will use whichever one works for this > purpose. I tried looking into the gem5 code to figure out how to do this, > however I encountered a big roadblock, since most of the code which deals > with instruction decoding and execution is generated by the compiler. I was > wondering if anyone knows a way to do this, or knows some reference of > someone who did prefetching research on gem5. Any help would be much > appreciated. > > Best regards, > Pedro Corrêa Rigotto > _______________________________________________ > gem5-users mailing list -- gem5-users@gem5.org > To unsubscribe send an email to gem5-users-le...@gem5.org >
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