Hi Ziyang, We don’t have a DSU model in gem5. If you are not interested in modelling the DSU per se and you are only interested on recreating a DSU-like system (a DynamIQ cluster), you can proceed as you suggested.
I also encourage you to have a look at the fs_bigLITTLE.py example script [1]; it can serve as a good starting point. Kind Regards Giacomo [1]: https://github.com/gem5/gem5/blob/stable/configs/example/arm/fs_bigLITTLE.py From: Peng, Ziyang via gem5-users <gem5-users@gem5.org> Date: Tuesday, 1 August 2023 at 04:11 To: gem5-users@gem5.org <gem5-users@gem5.org> Cc: Peng, Ziyang <ziyang.p...@intel.com> Subject: [gem5-users] Config ARM DSU in Gem5 simulator Hi all, I am a Gem5 user currently studying with the ARM architecture. In ARM, there is a DSU(DyanamIQ Shared Unit<https://developer.arm.com/documentation/100453/0401/The-DynamIQ-Shared-Unit/About-the-DSU>) comprises the L3 memory system, control logic, and external interfaces to support DynamIQ cluster. I would like to ask is there a way to configure DSU model in the Gem5 simulator or exist a more detailed ARM based configuration in Gem5? >From my understanding, I can config a L3Cache with a coherent XBar to simulate >the DSU part? Thanks + regards, Ziyang IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
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