Hi all, I am a Gem5 user currently studying with the ARM architecture. In ARM, there is a DSU(DyanamIQ Shared Unit<https://developer.arm.com/documentation/100453/0401/The-DynamIQ-Shared-Unit/About-the-DSU>) comprises the L3 memory system, control logic, and external interfaces to support DynamIQ cluster. I would like to ask is there a way to configure DSU model in the Gem5 simulator or exist a more detailed ARM based configuration in Gem5? >From my understanding, I can config a L3Cache with a coherent XBar to simulate >the DSU part?
Thanks + regards, Ziyang
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