Okay, but I've also noticed that a WriteReq generally carries no data. Why
exactly is that? Cause if we are writing to memory, then the memory access
latency shouldn't be 0 right?
On Tue, Jul 11, 2023 at 12:49 PM Eliot Moss <m...@cs.umass.edu> wrote:
> On 7/11/2023 12:37 PM, John Smith via gem5-users wrote:
> > Hi everyone,
> >
> > Could someone please help me with explaining what's happening in the
> below code snippet? It's the
> > receiveAtomicLogic() function in mem_ctrl.cc. Why are we returning the
> latency as 0 if the packet
> > doesn't have any data? And in what case will the packet have/not have
> data?
> >
> > // do the actual memory access and turn the packet into a response
> >
> > mem_intr->access(pkt);
> >
> >
> > if (pkt->hasData()) {
> >
> > // this value is not supposed to be accurate, just enough to
> >
> > // keep things going, mimic a closed page
> >
> > // also this latency can't be 0
> >
> > return mem_intr->accessLatency();
> >
> > }
> >
> >
> > return 0;
>
> John - Certain packets carry no data. For example, a cache line invalidate
> without write back will have that property. Maybe others.
>
> Best - Eliot
>
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