Hi, > -----Original Message----- > From: Burak Öçalan via gem5-users <gem5-users@gem5.org> > Sent: 27 July 2021 17:05 > To: gem5-users@gem5.org > Cc: Burak Öçalan <byrakocala...@gmail.com> > Subject: [gem5-users] Adding ArmTLB to prefetchers > > Hi. > > I'm working on Indirect Memory Prefetcher. This prefetcher requires a TLB to > work correctly. As far as I understand, I need to add the TLB manually. > > > In x86 simulations, I simply create a new X86TLB and give it to the prefetcher > in Prefetcher.py file. In SE mode it works, this is enough for the prefetcher > to > make functional translations. I didn't try FS mode but additional things must > be done I guess. > > > However, I can't do the same thing in ARM simulations. When I try to create a > new ArmTLB and give it to the prefetcher, it gives this error: > > fatal: fatal condition !stage2Mmu occurred: Table walker must have a valid > stage-2 MMU > > My question is; what is the correct way of adding TLB's to prefetchers for x86 > and ARM ISAs, which will work for both FS and SE simulations? > > Thanks a lot and have a great day.
You don't need to create a new TLB. You should rather link the prefetcher to the existing one (the mmu.dtb) As I am assuming you are using the stable branch, this means doing something like prefetcher = IndirectMemoryPrefetcher(...) prefetcher.registerTLB(cpu.mmu.dtb) Let me know if this works Kind regards Giacomo IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. _______________________________________________ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
