Hi. I'm working on Indirect Memory Prefetcher. This prefetcher requires a TLB to work correctly. As far as I understand, I need to add the TLB manually.
In x86 simulations, I simply create a new X86TLB and give it to the prefetcher in Prefetcher.py file. In SE mode it works, this is enough for the prefetcher to make functional translations. I didn't try FS mode but additional things must be done I guess. However, I can't do the same thing in ARM simulations. When I try to create a new ArmTLB and give it to the prefetcher, it gives this error: fatal: fatal condition !stage2Mmu occurred: Table walker must have a valid stage-2 MMU My question is; what is the correct way of adding TLB's to prefetchers for x86 and ARM ISAs, which will work for both FS and SE simulations? Thanks a lot and have a great day.
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