Thank you Maryam for the information. On Wed, Oct 21, 2020 at 6:51 AM Maryam Babaie <[email protected]> wrote:
> Hi Krishnan, > > As far as I probed, I can say: > 1. in the "system.cpu.itb_walker_cache" and "system.cpu.dtb_walker_cache", > the caches refer to TLB (instruction and data TLBs respectively). > 2. The walker refers to the page table walker. > 3. No page walk cache is implemented by gem5. > > Best Regards, > MB > > On Tue, Oct 20, 2020 at 4:45 PM Mahyar Samani <[email protected]> wrote: > >> >> >> ---------- Forwarded message --------- >> From: krishnan gosakan via gem5-users <[email protected]> >> Date: Tue, Oct 20, 2020 at 5:21 AM >> Subject: [gem5-users] Need clarification on few stat fields >> To: gem5 users mailing list <[email protected]> >> Cc: krishnan gosakan <[email protected]> >> >> >> Hi all, >> I hope you all are doing well. I have a doubt concerning the stat file >> generated for full system emulation. I see a lot of entries prefixed by >> "system.cpu.itb_walker_cache" and "system.cpu.dtb_walker_cache". I just >> want to know what caches are these referring to. Are they referring to TLB >> or Page Walk Cache? I would like to explore system performance with and >> without page walk cache. So, I want to know if page walk cache is already >> implemented in gem5. As far as I checked the pagetable_walker.cc, I don't >> see anything relevant to this. >> >> -- >> Regards, >> Krishnan. >> _______________________________________________ >> gem5-users mailing list -- [email protected] >> To unsubscribe send an email to [email protected] >> %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s >> >> >> -- >> Mahyar Samani (he/him/his) >> Electrical and Computer Engineering Department >> Research Assistant at *DArchR <https://arch.cs.ucdavis.edu/> (*2235 >> Kemper Hall) >> Secretary >> ECE-GSA >> Vice President >> Iranian Student Association at UC Davis >> University of California, Davis >> > -- Regards, Krishnan.
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