Hi Taya, There are 2 thresholds defined for this purpose: - write_high_thresh_perc - write_low_thresh_perc
The controller also has a parameter to define the minimum number of writes to issue once the bus has transitioned to the WRITE state. - min_writes_per_switch These are used to determine when the bus direction should switch from reads to writes in processNextReqEvent, where the next DRAM burst is selected. The accessAndRespond routine is called, as you indicated, when the command is placed in the Q for an early response upstream. This does not remove the entry from the Q, which will still be scheduled based on bus direction, QoS, DRAM timing, etc. The parameters listed above function as follows: Case1: Bus state is currently ‘READ’ Will switch to ‘WRITE’, enabling write bursts to issue from the writeQ if: * The read Q is empty, write Q is not empty and the number of writes in Q is greater than the LOW threshold (write_low_thresh_perc) OR * The number of writes in Q is greater than the HIGH threshold (write_high_thresh_perc) Case2: Bus state us currently ‘WRITE’ Will switch to ‘READ’, enabling read bursts to issue from the ReadQ if: * The writeQ is empty, OR * WriteQ is below the LOW threshold (using min_writes_per_switch as the hysteresis), OR * The read Q is not empty and the controller has issued min_writes_per_switch Thanks, Wendy From: gem5-users <gem5-users-boun...@gem5.org> on behalf of Taya <645505...@qq.com> Reply-To: gem5 users mailing list <gem5-users@gem5.org> Date: Monday, April 13, 2020 at 6:27 AM To: gem5-users <gem5-users@gem5.org> Subject: [gem5-users] WriteQueue inDramCtrl Hi guys！ I am trying to understand the DRAM in gem5.And I purpose is that stop writequeue flush untill it reach a setting threshold.So I look inside the source code abstract_mem.cc and dram_ctrl.cc. ,but can't understand on some place.In the function addToWriteQueue,it translate pkt to drampkt and then put it back to the writequeue according to qosvalue.After that ,addToWriteQueue call accessAndRespond which call function 'access' to perform a memory access and update some state for the pkt. These functions are confusing to me,because in my understanding memory controller need to put drampkt to WriteQueue and then access memory according to those drampkt in WriteQueue instead of adding drampkt to writeQueue and perform access(pkt) immediately. Is anyone familiar with this aspect. Give me some suggestion plz. Thanks! IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
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