Hi Jason, I went through the tutorial and understood quite a bit of it. What I understood is that, there is no usage of tags in the implementation, just an unordered map. So I thought with some changes in the latencies, I can create a tagless blocking cache. Is this a correct starting point in implementing tagless cache? or is there some thing more to it??
In order to try the idea out, I just changed the vector ports of the SimpleCache and tried to plug it as a second-level cache. The simulation stopped because of this reason, Exiting @ tick 18446744073709551615 because simulate() limit reached. To check out the I also used the simple cache, as it is, as a second-level cache in http://learning.gem5.org/book/part1/cache_config.html. And when I ran the simulation, this is what I encountered, info: Entering event queue @ 0. Starting simulation... panic: Unknown packet type! @ tick 9340000 [accessFunctional:build/X86/learning_gem5/simple_cache.cc, line 358] Memory Usage: 655584 KBytes Program aborted at tick 9340000 Kindly help me in this regard. Sorry for this long mail. Thank you Varun
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