Hi Yasir, gem5's ports are not as much of a physical model as they are a programming API. The "width" of the CPU->cache connection is determined by the CPU model (how many requests the CPU can issue per cycle) and the cache model (how many requests the cache can accept per cycle). The CPU (or any object) can send as many requests (as packets, see src/mem/packet.hh) across the port in a single cycle as it would like. The peer on the other side of the port (the cache in this case) is responsible for modeling contention and a "width". Similarly, if the port is connected to a crossbar, the crossbar code models a set bandwidth and the resulting contention.
Hope this clears it up. Cheers, Jason On Sat, Feb 4, 2017 at 6:01 AM Qureshi Yasir Mahmood <yasir.qure...@epfl.ch> wrote: Hello, When using L1 caches with a processor, in the config.ini file I can see that the cache is connected via system.cpu.dcache_port to the CPU side. I am unable to determine what is the size of the port. Does it depend on the CPU, e.g. if CPU is 32-bit then the port width for the CPU side of L1 is 32 and if it is 64-bit CPU then port width is 64 ? Regards Yasir _______________________________________________ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
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