Hello, When using L1 caches with a processor, in the config.ini file I can see that the cache is connected via system.cpu.dcache_port to the CPU side. I am unable to determine what is the size of the port. Does it depend on the CPU, e.g. if CPU is 32-bit then the port width for the CPU side of L1 is 32 and if it is 64-bit CPU then port width is 64 ?
Regards Yasir
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