Hi Debiprasanna, Thank you for your answer. I simulated CPU2006 with a single X86 core and SE mode. I started my simulation from a checkpoint I created before and used a switch "--standard-switch".
Why do you think MasterId is the "port number" of a cpu which issued a request? Do you find any comments about this? I thought each MasterId represents one unique kind of request, simply, it can differentiate different request types. But you mentioned the terminology "port number", it looks like a physical concept. Could you please explain it in more detail? I read all code related to MasterId, but can't find its any relation to a "port". Also, I remember port is a specific concept and is only used to connect different MemObject s, right? Thank you gjins On Sat, Mar 26, 2016 at 6:41 PM, Debiprasanna Sahoo < [email protected]> wrote: > Hi gjins, > > MasterId is the port number from which requested from the CPU. A CPU can > have a master ID for instruction (switch_cpu.inst) or data > (switch_cpu.data). > > Writebacks(wbMasterId) are also handled by a separate MasterId. The number > of master ids depends on the number of cores you are using for simulation. > > How many cores you are simulating? Are you using fast-forward options ? > > Regards, > Debiprasanna Sahoo > > On Sat, Mar 26, 2016 at 1:08 PM, Gongjin Sun <[email protected]> wrote: > >> Hi All, >> >> The MasterId is defined in src/mem/request.hh. There are four specific >> MasterIds: wbMasterId, funcMasterId, intMasterId and invldMasterId. >> According to some comments, MasterID is used to generate request. >> >> However, during my many simulations, I printed the size of MasterId >> (masterIds.size(), that is, the total of MasterIds) and found that the >> total number of MasterId in system are more than 4. For example, in one of >> my simulations, there are 18 MasterIds. One of them is 13, its MasterId's >> name is switch_cpus.data, and its request type is ReadReq. I am curious >> what kind of request is this. >> >> I thought most common requests we see should be covered by the above >> specific ones, like funcMasterId which should cover the usual demand >> read/write requests from cpu. So my confusion is why I still see so many >> (up to 18) MasterIds in my simulation? Besides the four specific ones, why >> do we still need other MasterIds and what are the rest uses for? >> >> In addition, are "all the ReadReq/WriteReq which are generated by cpu" >> demand requests just from load/store instructions? >> >> Any help are very appreciated. >> >> gjins >> >> >> >> _______________________________________________ >> gem5-users mailing list >> [email protected] >> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >> > > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >
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