Hi All, The MasterId is defined in src/mem/request.hh. There are four specific MasterIds: wbMasterId, funcMasterId, intMasterId and invldMasterId. According to some comments, MasterID is used to generate request.
However, during my many simulations, I printed the size of MasterId (masterIds.size(), that is, the total of MasterIds) and found that the total number of MasterId in system are more than 4. For example, in one of my simulations, there are 18 MasterIds. One of them is 13, its MasterId's name is switch_cpus.data, and its request type is ReadReq. I am curious what kind of request is this. I thought most common requests we see should be covered by the above specific ones, like funcMasterId which should cover the usual demand read/write requests from cpu. So my confusion is why I still see so many (up to 18) MasterIds in my simulation? Besides the four specific ones, why do we still need other MasterIds and what are the rest uses for? In addition, are "all the ReadReq/WriteReq which are generated by cpu" demand requests just from load/store instructions? Any help are very appreciated. gjins
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