hello,kumail,
you can reference the original configure file of cache, namely
config/common/CacheConfigure.py , l2 cache is shared among all cpus in the
unmodified cacheconfig.py , and the l1 caches are all private. You can create a
"l3 cache" and a "l3 cache bus" based on the BaseCache and CoherentBus，and
define the l3 cache's cpu_side and mem_side . You can find the detailed answer
on the Internet.
by the way , I'm also confused about how to share 2 l2 caches between 4
cores : two cpus share one l2 cache. You said you make it , how do you make it
! I'll appreciate it if you response me! Thanks very much!
--
YujieChen
School of Computer Science and Technology
Cluster and Grid Computing Lab
Services Computing Technology and System Lab
Huazhong University of Science and Technology
Wuhan, 430074, China
Email:[email protected]
At 2014-11-11 21:01:32, "Kumail Ahmed via gem5-users" <[email protected]>
wrote:
Thank you very much andreas :) I did it!
Can you tell me how I can add l3cache in the classical memory model? Do I have
to create a new l3cache class can share it on the l2 bus?
Thanks again,
Kumail Ahmed
Masters Student
TU Kaiserslautern, Germany
On Tue, Nov 11, 2014 at 1:56 PM, Andreas Hansson <[email protected]>
wrote:
Hi Kumail,
The crossbar in gem5 supports address striping, so you can create a “toL2Bus”
that interleaves between two L2 caches. Have a look at
config/common/MemConfig.py for how the interleaving is configured (for the
memory channels). You should be able to do something similar.
Andreas
From: Kumail Ahmed via gem5-users <[email protected]>
Reply-To: Kumail Ahmed <[email protected]>, gem5 users mailing list
<[email protected]>
Date: Tuesday, 11 November 2014 10:45
To: "[email protected]" <[email protected]>
Subject: [gem5-users] Sharing L2 cache
Hello,
How an I share two L2 caches between 4 CPU cores in GEM5. I guess I have to
change the code in Cacheconfig.py.
Can someone help me with this?
Thanks,
Kumail Ahmed
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