Hi Kumail,
The crossbar in gem5 supports address striping, so you can create a “toL2Bus”
that interleaves between two L2 caches. Have a look at
config/common/MemConfig.py for how the interleaving is configured (for the
memory channels). You should be able to do something similar.
Andreas
From: Kumail Ahmed via gem5-users
<[email protected]<mailto:[email protected]>>
Reply-To: Kumail Ahmed <[email protected]<mailto:[email protected]>>, gem5
users mailing list <[email protected]<mailto:[email protected]>>
Date: Tuesday, 11 November 2014 10:45
To: "[email protected]<mailto:[email protected]>"
<[email protected]<mailto:[email protected]>>
Subject: [gem5-users] Sharing L2 cache
Hello,
How an I share two L2 caches between 4 CPU cores in GEM5. I guess I have to
change the code in Cacheconfig.py.
Can someone help me with this?
Thanks,
Kumail Ahmed
-- IMPORTANT NOTICE: The contents of this email and any attachments are
confidential and may also be privileged. If you are not the intended recipient,
please notify the sender immediately and do not disclose the contents to any
other person, use it for any purpose, or store or copy the information in any
medium. Thank you.
ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered
in England & Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ,
Registered in England & Wales, Company No: 2548782
_______________________________________________
gem5-users mailing list
[email protected]
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
