Thanks for your help Andreas. I'll try the DDR3 private instance in the WIO controller and see how that goes.
Andreas Prodromou On Sat, Aug 9, 2014 at 9:13 AM, Andreas Hansson <[email protected]> wrote: > Hi Andreas, > > You can have as many (different) DRAM controllers as you want, but they > are currently all sub-classes of AbstractMemory, and as such they are all > responsible for a unique address range. In other words, they sit next to > each other rather than above/below each other. You can always hack a sort > of cache controller in front of two DRAM controllers and use the WIO range > as a kind of cache, but it will be a rather invasive change and rather > invasive. > > The only “simple” hack I can think of would be to have the WIO be the > system-visible DRAM controller responsible for the entire DDR3 range, and > then inside the WIO controller instantiate another private instance (or as > many channels as you want) that is not in the system memory range, and then > internally call the latter for fills/writebacks. The DDR3 controller would > then not be visible in the system memory map. It will be messy though. > > Andreas > > From: Andreas Prodromou <[email protected]> > Date: Saturday, August 9, 2014 at 3:55 PM > To: Andreas Hansson <[email protected]>, gem5 users mailing list < > [email protected]> > Subject: Re: [gem5-users] How to model on-chip DRAM? > > Hi Andreas and thanks for your quick response, > > I actually want to evaluate memory controller optimizations for that > system, so I cannot fake the DRAM by changing cache parameters. Is there > any way to have more than one DRAM memories in the same system? > > Andreas Prodromou > > > On Sat, Aug 9, 2014 at 4:45 AM, Andreas Hansson <[email protected]> > wrote: > >> Hi Andreas, >> >> Your best option here is to tune the existing cache model, and set the >> latencies appropriately. Note that gem5 currently assumes a unified >> cache-line size throughout the memory system, so you end up having to use >> e.g. 64 byte cache lines also for the DRAM cache. The most important >> question you have to answer in tuning the parameters is how/where you place >> the tags. >> >> I hope that helps. >> >> Andreas >> >> From: Andreas Prodromou via gem5-users <[email protected]> >> Reply-To: Andreas Prodromou <[email protected]>, gem5 users >> mailing list <[email protected]> >> Date: Friday, August 8, 2014 at 11:09 PM >> To: gem5 users mailing list <[email protected]> >> Subject: [gem5-users] How to model on-chip DRAM? >> >> Hello everybody, >> >> I'm trying to model on-chip DRAM that acts as the last level cache. The >> system I want to model has four WideIO controllers for the on-chip DRAM and >> two DDR3 controllers for the off-chip DRAM. >> >> I tried to add the on-chip memory controllers the same way I would add >> a shared L3 cache in the CacheConfig.py but no luck so far. Does anybody >> have any pointers? >> >> Thanks, >> Andreas Prodromou >> >> -- IMPORTANT NOTICE: The contents of this email and any attachments are >> confidential and may also be privileged. If you are not the intended >> recipient, please notify the sender immediately and do not disclose the >> contents to any other person, use it for any purpose, or store or copy the >> information in any medium. Thank you. >> >> ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, >> Registered in England & Wales, Company No: 2557590 >> ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, >> Registered in England & Wales, Company No: 2548782 >> > > > -- IMPORTANT NOTICE: The contents of this email and any attachments are > confidential and may also be privileged. If you are not the intended > recipient, please notify the sender immediately and do not disclose the > contents to any other person, use it for any purpose, or store or copy the > information in any medium. Thank you. > > ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, > Registered in England & Wales, Company No: 2557590 > ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, > Registered in England & Wales, Company No: 2548782 >
_______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
