Hi Andreas,
Your best option here is to tune the existing cache model, and set the
latencies appropriately. Note that gem5 currently assumes a unified cache-line
size throughout the memory system, so you end up having to use e.g. 64 byte
cache lines also for the DRAM cache. The most important question you have to
answer in tuning the parameters is how/where you place the tags.
I hope that helps.
Andreas
From: Andreas Prodromou via gem5-users
<[email protected]<mailto:[email protected]>>
Reply-To: Andreas Prodromou
<[email protected]<mailto:[email protected]>>, gem5 users
mailing list <[email protected]<mailto:[email protected]>>
Date: Friday, August 8, 2014 at 11:09 PM
To: gem5 users mailing list <[email protected]<mailto:[email protected]>>
Subject: [gem5-users] How to model on-chip DRAM?
Hello everybody,
I'm trying to model on-chip DRAM that acts as the last level cache. The system
I want to model has four WideIO controllers for the on-chip DRAM and two DDR3
controllers for the off-chip DRAM.
I tried to add the on-chip memory controllers the same way I would add a shared
L3 cache in the CacheConfig.py but no luck so far. Does anybody have any
pointers?
Thanks,
Andreas Prodromou
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