Hi Sophiane, By the time you look a the write packet it has already been responded to and consequently deleted. When a write arrives we put it in the write queue and send the response straight away. If you want to know if the DRAMPacket is a write look at dram_pkt->isRead. It¹s worth noting that adding latency to the writes will probably not have any impact for the very reason stated above.
Andreas On 04/11/2013 13:45, "senni sophiane" <[email protected]> wrote: >Hi everybody, > >I am trying to differentiate latency for read and write access in >SimpleDRAM adding a new parameter tCL_write. >When I use a " if(dram_pkt->pkt->isWrite()) " statement in >simple_dram.cc (function SimpleDRAM::estimateLatency), I have a >segmentation fault when booting in FS or SE mode. > >I don't know what is the problem. Does someone have an idea why it >doesn't work ? > >Thank you. > >-- >Cordialement / Best Regards > >SENNI Sophiane >Ph.D. candidate - Microelectronics >LIRMM - www.lirmm.fr > >_______________________________________________ >gem5-users mailing list >[email protected] >http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2557590 ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2548782 _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
