Hi everybody,
I am trying to differentiate latency for read and write access in
SimpleDRAM adding a new parameter tCL_write.
When I use a " if(dram_pkt->pkt->isWrite()) " statement in
simple_dram.cc (function SimpleDRAM::estimateLatency), I have a
segmentation fault when booting in FS or SE mode.
I don't know what is the problem. Does someone have an idea why it
doesn't work ?
Thank you.
--
Cordialement / Best Regards
SENNI Sophiane
Ph.D. candidate - Microelectronics
LIRMM - www.lirmm.fr
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