Thanks for your reply,
I am using only one core (ARM O3). And I am using the classic memory
system. I want to know if there is something in the classic memory
system that can hide the write latency (if it is high).
I figured out that mshrs and writebuffers are used for read and write
misses. And in the wiki, cache model in classic memory system is
described as a non-blocking cache.
Also, If I understood, I think that number of accesses per cycle for
cache memory is unlimited or very high. Am I right ?
So, I am trying to understand how exactly classic memory system works
and hence, what can I do to make my system sensitive to read and write
latency (particularly to write latency).
Why I want to do this ? I am working on emerging memory technologies
which have different read and write latency.
If someone has some suggestions, please tell me.
Of course, when this work will be done and validated, I plan to post a
patch for gem5 users who are interested.
Le 25/10/2013 16:43, Fernando Endo a écrit :
Hello,
I'm not a cache expert, but it depends if you have or not reads after
the writes, and if other cores use them. The writes can be queued in
the cache controller, but the read will definitively block its
dependencies in the cpu.
Regards,
--
Fernando A. Endo, PhD student and researcher
Université de Grenoble, UJF
France
2013/10/24 senni sophiane <[email protected]
<mailto:[email protected]>>
Hi everybody,
I ran some simulations increasing the write latency (only) for
caches (L1 and L2) but there is no significant impact on execution
time (sim_seconds in stats.txt).
But when I increase read latency (only) for caches, significant
change on sim_seconds can be noticed.
Is it normal ? If yes, why ? And how can I include the effect of
write latency into the running application ?
Thanks
Sophiane
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