Hello, I'm not a cache expert, but it depends if you have or not reads after the writes, and if other cores use them. The writes can be queued in the cache controller, but the read will definitively block its dependencies in the cpu.
Regards, -- Fernando A. Endo, PhD student and researcher Université de Grenoble, UJF France 2013/10/24 senni sophiane <[email protected]> > Hi everybody, > > I ran some simulations increasing the write latency (only) for caches (L1 > and L2) but there is no significant impact on execution time (sim_seconds > in stats.txt). > But when I increase read latency (only) for caches, significant change on > sim_seconds can be noticed. > > Is it normal ? If yes, why ? And how can I include the effect of write > latency into the running application ? > > Thanks > > Sophiane > ______________________________**_________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/**mailman/listinfo/gem5-users<http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users> >
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