Hi Ahmad,
Doing address decoding based on virtual addresses in the interconnect (which is
what you suggest), is something I would greatly advise against. If you really
want to do this, the place you need to hack (i.m.h.o) is the Bus base class.
The function findPort determines where to route the packet based on the
physical address.
Once again, I would advise against using anything but the physical address for
the address decoding, and rather make sure your physical page mapping does what
you want.
Andreas
From: Ahmad Hassan <[email protected]<mailto:[email protected]>>
Date: Friday, 25 October 2013 11:40
To: Andreas Hansson <[email protected]<mailto:[email protected]>>
Cc: gem5 users mailing list <[email protected]<mailto:[email protected]>>
Subject: Re: Running two SimpleDram instances simulataniously
If you want to control the virtual to physical mapping, I am afraid you have to
figure out a way to control the page allocation in the OS. Perhaps someone on
the list knows a sensible way of achieving this without too much Linux brain
surgery.
OS is not required. In my case, I have the list of virtual address which I know
that they should always go through DDR3 timing model and the rest of the
virtual addresses should go to PCM timing model. In the integrated patch of
dramsim2 with GEM5 it was trivial where I added this logic in
"DRAMSim2::MemoryPort::recvTimingReq". I instantiated two instances of dramsim2
(one with DDR3 timing and second with PCM timing). Then in recvTimingReq method
I was checking the incoming virtual address and then calling appropriate
dramsim2 instance accordingly.
I want to do similar thing with SimpleDRAM model of Gem5. Is it possible?
Thanks.
kind Regards, Ahmad
Andreas
From: Ahmad Hassan <[email protected]<mailto:[email protected]>>
Date: Friday, 25 October 2013 11:18
To: Andreas Hansson <[email protected]<mailto:[email protected]>>,
gem5 users mailing list <[email protected]<mailto:[email protected]>>
Subject: Re: Running two SimpleDram instances simulataniously
Thanks Andreas for the details. As I want to add a logic of which virtual
addresses should go to which memory controller (DDR3 or PCM), so I was thinking
that I would have one memory port that receives packet from the system and then
I add up logic of virtual address and call the appropriate memory controller
(DDR3 or PCM) afterwards. Do you suggest the same?
Otherwise if we add two memory controller ports to the memory bus then what
place would I add the logic of which virtual address should go to which
controller?
CC'ing user list.
Thanks.
Best Regards, Ahmad
On 24 October 2013 19:28, Andreas Hansson
<[email protected]<mailto:[email protected]>> wrote:
Hi Ahmad,
You can instantiate as many controller as you want, all you have to do is edit
the python files. You can either try and add it as an option to fs.py or
similar, or manually create a system in a separate .py file.
You can simply do system.ddr3_ctrl = SimpleDDR3() and system.pcm_ctrl =
SimplePCM() (you have to create the latter class). You pass the address range
as a parameter to each controller. When you connect them to the bus they will
automatically be updating the address map in the bus.
Good luck.
As a final note, please stick to the mailing list :-)
Andreas
From: Ahmad Hassan <[email protected]<mailto:[email protected]>>
Date: Wednesday, 23 October 2013 20:29
To: Andreas Hansson <[email protected]<mailto:[email protected]>>
Subject: Re: Running two SimpleDram instances simulataniously
Or more simply, how would it be possible to use both "SimpleLPDDR2_S4" and
"SimpleDDR3" simultaneously. I will redirect some virtual addresses to
SimpleLPDDR2_S4 and some to SimpleDDR3.
Thanks.
kind Regards, Ahmad
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in England & Wales, Company No: 2557590
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Registered in England & Wales, Company No: 2548782
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