Specifically for ARM L1/L2 caches using the default memory, e.g.: ./build/ARM/gem5.fast ... configs/example/fs.py ... --caches --cpu-type=detailed --l1d_size=32kB --l1i_size=32kB --l2cache --l2_size=2048kB --clock=0.75GHz
How is each cache configured in terms of banks? Is each the L1d, L1i and L2 cache a single memory bank by default? I've looked through the gem5/ directory but couldn't find any mention of bank configurations except for specific memory protocols or for DRAM. And couldn't find any mention of this elsewhere. Thank you, Gabriel
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