Hello,
I'm trying to modify a cache on the memory system hierarchy to be able
to not to store certain requests, and therefore, act as a bypass cache
for those packets.
I added an extra condition to every " if (system->bypassCaches()) "
condition on /cache_impl.hh/ file to recognize those packets and don't
store them. When running in functional mode it works out well, but when
in timing mode it results on a panic message saying:
panic: Packet ReadReq already has bus delay (1000, 500) that should be
accounted for.
If I force those delays to 0 by doing:
"pkt->busFirstWordDelay = pkt->busLastWordDelay = 0;"
The method /recvTimingResp/ doesn't find the a valid mshr and fails on
the assertion.
How can I get this solved? What am I missing? Have I to change the
initial approach of using the bypassCaches condition extended?
Thanks!
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