Ok thank you for the clarification. I just need correct behavior, so I have no intention adding this functionality to Gem5.
Best, Samuel On Tue, Apr 24, 2012 at 3:48 PM, Anthony Gutierrez <atgut...@umich.edu>wrote: > That's correct you don't have to worry about cache maintenance. No, the > d-cache is not write-through. It doesn't need to be. > > I have some patches for the i-cache maintenance operations (mcr icimvau, > icialluis) and the d-cache wouldn't be difficult to implement using these > as a base. They implement them functionally, but provide no realistic > timing information. You could start with them as a base. However, unless > you want to study the behavior of these types of instructions they're not > really necessary because, as Ali pointed out, the simulator maintains > coherence in the i-cache. > > -Tony > > On Tue, Apr 24, 2012 at 9:28 AM, Ali Saidi <sa...@umich.edu> wrote: > >> ** >> >> Hi Samuel, >> >> >> >> The invalidations aren't needed for correctness, gem5 supports i cache >> snooping of invalidates and that is a perfectly acceptable thing to do from >> an architecture perspective. If you want to implement cache >> flushing/invalidation you'll first need to add the ability to do that to >> the caches and then connect the generation of the method you create to the >> arm instructions. It will take a fair amount of work to do. >> >> >> >> Ali >> >> >> >> On 24.04.2012 13:45, Samuel Hitz wrote: >> >> Hi there, >> How can I clean/invalidate I- and D-cache on your ARM implementation? It >> seems that many cache maintenance operations are not supported. Could >> someone help me with this? >> Best, >> Samuel >> >> >> >> >> _______________________________________________ >> gem5-users mailing list >> gem5-users@gem5.org >> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >> > > > _______________________________________________ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >
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