On Fri, 2 Mar 2012, Jiachen Xue wrote:
Hi Nilay,
In ALPHA, the TLB miss is handled by software. If there is TLB miss, a
fault is set and the OS inserts a new entry into the TLB using PAL routine.
When using O3 cpu, in the case of ITB miss, if a TLB miss is detected, a
noop instruction is constructed within finishTranslation routine located at
cpu/o3/fetch_impl.hh:664, and then at commit stage, the commitInst function
at cpu/o3/commit_impl.hh:1024 calls updateMiscRegs at cpu/dyn_inst.hh:184,
and eventually, the setIpr function located at arch/alpha/ev5.cc:407 will
be called to insert an new entry to the TLB.
Thanks,
Jiachen Xue
On Fri, Mar 2, 2012 at 2:35 PM, Nilay Vaish <[email protected]> wrote:
On Fri, 2 Mar 2012, Jiachen Xue wrote:
Hello all,
I am using ALPHA FS and O3 cpu model, and I am trying to modify the code
to
add a second level TLB.
My first question is, take the instruction TLB as an example, in the
original implementation, if there is a TLB miss
during the fetch stage, a noop instruction will be built and the fault
will
be handled during the commit stage using
OS traps. Does this mean I need to modify both TLB and CPU code to include
a second level TLB?
Secondly, how to handle the timing changes when a second level TLB is
added?
Can you explain how ALPHA architecture handles TLB misses? This might help
in understanding where should the changes go in.
So there are two things that need to be done. First, in case of L1 TLB
miss and L2 TLB hit, the PAL code should be able to insert an entry in to
the L1 TLB. Second, the case of L2 TLB miss, the pal code should be able
to insert an entry into the L2 TLB.
On second thought, it seems that the L1 TLB miss will not be handled by
the PAL code, and that some hardware mechanism will insert the entry from
the L2 TLB to the L1 TLB.
I think the O3 CPU will not change. Instead, the current L1 TLB will act
as the L2 TLB and the PAL code will only come into picture if there is an
L2 TLB miss. What you need is a new L1 TLB that gets filled in from the L2
TLB on a miss.
Does this make sense?
--
Nilay
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