Hello all, I am using ALPHA FS and O3 cpu model, and I am trying to modify the code to add a second level TLB.
My first question is, take the instruction TLB as an example, in the original implementation, if there is a TLB miss during the fetch stage, a noop instruction will be built and the fault will be handled during the commit stage using OS traps. Does this mean I need to modify both TLB and CPU code to include a second level TLB? Secondly, how to handle the timing changes when a second level TLB is added? Thanks, Jiachen -- Sincerely, Jiachen Xue
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